Curriculum Vitae

Saman Prabhath Amarasinghe

Internet: 

saman@lcs.mit.edu
http://compiler.lcs.mit.edu/~saman

Postal:

NE43-620B
Laboratory for Computer Science, 
200 Technology Square,
Cambridge, MA 02139 

Telephone: 

(617) 253-8879 (office)
(617) 253-1221 (fax) 
(781) 891-0816 (home)

ACADEMIC AND RESEARCH EXPERIENCE

Professor, Massachusetts Institute of Technology, Cambridge, MA

July 2009 - present

Associate Professor, Massachusetts Institute of Technology, Cambridge, MA

July 2001 - June 2009

Assistant Professor, Massachusetts Institute of Technology, Cambridge, MA

February 1997 - June 2001

Department of Electrical Engineering and Computer Science and Laboratory for Computer Science

Leader of the Commit Group and co-leader of the RAW project. Research interest include compiler algorithms, computer architecture and parallel processing. Interested in discovering novel approaches to improve the performance of modern computer systems without unduly increasing the complexity faced by either application developers, compiler writers or computer architects. 

 

Research Assistant, Stanford University, Stanford CA

January 1990 - January 1997

Performed research in parallelizing compilers and parallel architectures. Participated in the design and implementation of the SUIF compiler system, a publicly available parallelizing and optimizing compiler system that is specifically designed to support research and rapid prototyping. SUIF is currently used at many universities and companies. 

 

Teaching Assistant, Western Institute of Computer Science, Stanford, CA

Summers 1991, 1992

Planned and conducted sections for a parallel architectures and compilers course for professionals.

PROFESSIONAL EXPERIENCE

CTO, Determina, Inc., Redwood City, CA

June 2003 - present

 Co-founded Determina to bring the Host Intrusion Prevention technology (Program Shepherding) developed at MIT to the market.  

 

Member, Technical Advisory Board, Millennium Information Technologies, Cambridge, MA

July 2001 - present

 Technical Advisor. 

 

Consultant, Delta Search Labs. Cambridge, MA

June 2001 - December 2001

Technical Advisor. 

 

Consultant, McDonell Boehnen Hulbert and Berghoff, Chicago, IL

March 2000 - June 2000

Expert Witness. 

 

Director, Lanka Internet Services, Ltd. Colombo, SRI LANKA

January 1994 - June 2001

Co-founded the first internet service provider in Sri Lanka. Was involved in all aspects of the start-up process and served as the primary technical advisor. 

 

Independent Consultant, Thinking Machines Corporation, Boston, MA

February 1994

Parallel Compiler Group
Helped formulate the communication optimization and code generation strategy for the HPF compiler. 

 

Software Engineer, Stanford University, Stanford, CA

September 1988 - December 1989

Networking and Communication Systems
Designed, developed, and maintained a TCP/IP protocol stack and related software for PCs. 

 

Development Engineer, Microsoft Corporation, Redmond, WA 

Summers 1988, 1989

LAN Manager group
Developed OS/2 kernel debugger extensions, analyzed and improved the LAN Manager server performance, and participated in the debugging process of the server. Helped start internationalization process of the LAN Manager family of products. 

 

Programmer / Analyst, Cornell University, Ithaca, NY

January 1986 - June 1988

Engineering Placement Office
Designed, developed, and maintained a national award-winning software package to handle the interview sign-up and scheduling process. 

 

Technical Consultant, Cornell University, Ithaca, NY

August 1987 - June 1988

Career Center
Planned the automation strategy for the center and its library. 

 

Co-op Engineer, Xerox Corporation, Webster, NY

Summer 1986,
August - December 1985

High Volume Product Development Reprographics Business Group
Developed device drivers and evaluated the use of hard drives to store real-time scanned data. Designed and developed a control system for a xerographic sub-system of a test fixture.

EDUCATION

Doctor of Philosophy in Electrical Engineering
Stanford University, Stanford, CA 

January 1997

Master of Electrical Engineering
Stanford University, Stanford, CA

June 1990

Bachelor of Science
Cornell University, Ithaca, NY
Majors: Electrical Engineering and Computer Science 

May 1988

University of Moratuwa, Moratuwa, Sri Lanka

January 1984 - June 1984

G.C.E. A/L
Royal College, Colombo, Sri Lanka

1972 - 1982

Grade 2
Thurston Junior, Colombo, Sri Lanka

1970 - 1971

AWARDS AND HONORS

InfoWorld Innovator 2005 Award, InfoWorld Magazine

IBM Eclipse Innovation Award.

Arthur Samuel Best PhD Thesis Award, Computer Science Dept., Stanford University

CIS Fellowship from Intel Corporation

Eta Kappa Nu

Tau Beta Pi

Phi Kappa Phi

PROFESSIONAL ACTIVITIES

Program Committee Member:
ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2004.
36th Annual International       Symposium on Microarchitecture(Micro), 2003.
The Twelfth International Conference on Parallel Architectures and Compilation Techniques (PACT), 2003.
First Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 2003.
35th Annual International       Symposium on Microarchitecture(Micro), 2002.
16th Annual International Conference on Supercomputing (ICS), 2002.
6th Workshop on Languages, Compilers, and Run-time Systems for Scalable Computers (LCR), 2002.
29th Annual International Symposium on Computer Architecture (ISCA), 2002.
34th Annual International  Symposium on Microarchitecture (Micro)  2001.
Ninth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2000.
27th Annual International Symposium on Computer Architecture (ISCA), 2000.
ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 2000.
Eleventh IASTED International Conference on Parallel and Distributed Computing and Systems, 1999.
High Performance Networking and Computing Conference(SC99), 1999.
Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 1998.

Associate Editor:  ACM Transactions on Architecture and Code Optimization, 2003 to 2006.

Co-chairman: The First Workshop on Streaming Systems, 2003.

Reviewer: IEEE Transactions on Parallel and Distributed Systems, ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), ACM SIGPLAN Conference on Principles and Practice of Parallel Programming (PPoPP), ACM SIGPLAN Conference on Object-Oriented Programming Systems, Languages, and Applications (OOPSLA), Supercomputing, and Symposium on the Frontiers of Massively Parallel Computation.

Member: Technical Advisory Committee, University of Colombo School of Computing, Colombo, Sri Lanka

PUBLICATIONS

The most up-to-date list of publications can be found HERE

Journal Articles, Refereed Conference and Workshop Papers

2006

  1. Exploiting Coarse-Grained Task, Data, and Pipeline Parallelism in Stream Programs.
    Michael Gordon, William Thies, and Saman Amarasinghe
    In In Proceedings of the Twelfth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), San Jose, CA, October, 2006.

 

  1. Abstraction Layers for Scalable Microfluidic Biocomputers.
    William Thies, John Paul Urbanski, Todd Thorsen and Saman Amarasinghe
    In Proceedings of the 12th International Meeting on DNA Computing (DNA 2006), Seoul, Korea, June, 2006.

 

  1. MPEG-2 Decoding in a Stream Programming Language.
    Matthew Drake, Henry Hoffman, Rodric Rabbah, and Saman Amarasinghe
    In Proceedings of the 20th IEEE International Parallel & Distributed Processing Symposium, Rhodes Island (IPDPS), Rhodes Island, Greece, April, 2006.

 

  1. Digital microfluidics using soft lithography..
    John Paul Urbanski, William Thies, Christopher Rhodes, Saman Amarasinghe, and Todd Thorsen,
    In Lab on a Chip, January, 2006, 6(1), pp. 96-104.

 

2005

  1. Exploiting Vector Parallelism in Software Pipelined Loops.
    Samuel Larsen, Rodric Rabbah, and Saman Amarasinghe.
    In Proceedings of the 38th International Symposium on Microarchitecture (Micro), Barcelona, Spain, November, 2005.

 

  1. Convergent Scheduling.
    Diego Puppin, Mark Stephenson, Walter Lee, and Saman Amarasinghe.
    In Journal of Instruction-Level Parallelism (JILP), September, 2005.

 

  1. Optimizing Stream Programs Using Linear State Space Analysis.
    Sitij Agrawal, William Thies, and Saman Amarasinghe.
    In Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), San Francisco, September, 2005.

 

  1. High-Productivity Stream Programming For High-Performance Systems.
    Rodric Rabbah, Bill Thies, Michael Gordon, Janis Sermulins, and Saman Amarasinghe.
    In Proceedings of the Ninth Annual High Performance Embedded Computing Workshop (HPEC), Lincoln, MA, September 2005.

 

  1. Teleport Messaging for Distributed Stream Programs.
    William Thies, Michal Karczmarek, Janis Sermulins, Rodric Rabbah, and Saman Amarasinghe.
    In Proceedings of ACM SIGPLAN 2005 Symposium on Principles and Practice of Parallel Programming (PPoPP), Chicago, Illinois, June, 2005.

 

  1. Cache Aware Optimization of Stream Programs.
    Janis Sermulins, William Thies, Rodric Rabbah, and Saman Amarasinghe.
    In Proceedings of the 2005 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), Chicago, Illinois, June, 2005.

 

  1. Language and Compiler Design for Streaming Applications .
    Saman Amarasinghe, Michael I. Gordon, Michal Karczmarek, Jasper Lin, David Maze, Rodric M. Rabbah, and William Thies.
    In International Journal of Parallel Programming, Vol. 33, Nos. 2/3, June 2005.

 

  1. Maintaining Consistency and Bounding Capacity of Software Code Caches.
    Derek Bruening and Saman Amarasinghe.
    In Proceedings of the 3rd International Symposium on Code Generation and Optimization (CGO), San Jose, California, March, 2005.

 

  1. Predicting Unroll Factors Using Supervised Classification.
    Mark Stephenson and Saman Amarasinghe.
    In Proceedings of the 3rd International Symposium on Code Generation and Optimization (CGO), San Jose, California, March, 2005.

 

  1. A Productive Programming Environment for Stream Computing.
    Kimberly Kuo, Rodric Rabbah, and Saman Amarasinghe.
    In Second Workshop on Productivity and Performance in High-End Computing, San Francisco, California, February, 2005.

 

  1. Scalar Operand Networks.
    Michael Bedford Taylor, Walter Lee, Saman Amarasinghe, and Anant Agarwal.
    In Transactions on Parallel and Distributed Systems (Special Issue on On-chip Networks), February 2005.

 

2004

  1. Convergent Scheduling.
    Diego Puppin, Mark Stephenson, Walter Lee, Saman Amarasinghe.
    In Journal of Instruction-Level Parallelism, Volume 6, September 2004.

 

  1. Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams.
    Michael Taylor, Walter Lee, Jason Miller, David Wentzlaff, Ian Bratt, Benjamin Greenwald, Henry Hoffman, Paul Johnson, Jason Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew Frank, Saman Amarasinghe, and Anant Agarwal.
    In Proceedings of the 31st Annual International Symposium on Computer Architecture (ISCA), Munich, Germany, June, 2004.

 

2003

  1. Adapting Convergent Scheduling Using Machine-Learning,
    Diego Puppin, Mark Stephenson, Una-May O'Reilly, Martin C. Martin, and Saman Amarasinghe,
    In Proceedings of the 16th International Workshop on Languages and Compilers for Parallel Computing (LCPC), College Station, Texas, October 2003.

 

  1. High-Bandwidth Packet Switching on the Raw General-Purpose Architecture,
    Gleb A. Chuvpilo and Saman Amarasinghe
    In Proceedings of the International Conference on Parallel Processing (ICPP), Kaohsiung, Taiwan, Republic of China, October 2003.

 

  1. Linear Analysis and Optimization of Stream Programs,
    Andrew Lamb, William Thies, Saman Amarasinghe,
    In Proceedings of the SIGPLAN '03 Conference on Programming Language Design and Implementation (PLDI), San Diego, California, June 2003.

 

  1. Meta Optimization: Improving Compiler Heuristics with Machine Learning,
    Mark Stephenson, Una-May O'Reilly, Martin C. Martin, and Saman Amarasinghe,
    In Proceedings of the SIGPLAN '03 Conference on Programming Language Design and Implementation (PLDI), San Diego, California, June 2003.

 

  1. Phased Scheduling of Stream Programs,
    Michal Karczmarek, William Thies, Saman Amarasinghe,
    In     Proceedings of the ACM SIGPLAN '03 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), San Diego, California, June 2003.

 

  1. Dynamic Native Optimization of Interpreters,
    Gregory Sullivan, Derek Bruening, Iris Baron, Timothy Garnett, Saman Amarasinghe,
    In Proceedings of the ACM SIGPLAN '03 Workshop on Interpreters, Virtual Machines and Emulators (IVME), San Diego, California, June 2003.

 

  1. Genetic Programming Applied to Compiler Heuristic Optimization, 
    Mark Stephenson, Una-May O'Reilly, Martin C. Martin, and Saman Amarasinghe,
    In Proceedings of the 6th European Conference on Genetic Programming (EuroGP),Essex, UK, April, 2003.

 

  1. Defying the Speed of Light: Wire-Exposed Architectures and Spatially-Aware Compilers,
    Saman Amarasinghe.
    In Proceedings of the 28th Annual GOMACTech Conference, Tampa, Florida, March, 2003.

 

  1. An Infrastructure for Adaptive Dynamic Optimization,
    Derek Bruening, Timothy Garnett, Saman Amarasinghe,
    In Proceedings of the First Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO), San Francisco, California, March 2003.

 

  1. Scalar Operand Networks,
    Michael Bedford Taylor, Walter Lee, Saman Amarasinghe, and Anant Agarwal,
    In Proceedings of the Ninth International Symposium on High Performance Computer Architecture (HPCA), Anaheim, California, February, 2003.

 

  1. A 16-issue multiple-program-counter microprocessor with point-to-point scalar operand network,
    M. B. Taylor, J. Kim, J. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffman, P. Johnson, W. Lee, A. Saraf, N. Shnidman, V. Strumpen, S. Amarasinghe, A. Agarwal.
    In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, California, February, 2003.

 

2002

  1. Convergent Scheduling,
    Walter Lee, Diego Puppin, Shane Swanson, Saman Amarasinghe,
    In Proceedings of the 35th Annual International Symposium on Microarchitecture (MICRO), Istanbul, Turkey, November 2002.

 

  1. A Stream Compiler for Communication-Exposed Architectures, (detailed results)
    Michael Gordon, William Thies, Michal Karczmarek, Jasper Lin, Ali S. Meli, Chris Leger, Andrew A. Lamb, Jeremy Wong, Henry Hoffman, David Z. Maze, and Saman Amarasinghe,
    In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), San Jose, CA, October 2002.

 

  1. Increasing and Detecting Memory Address Congruence,
    Sam Larsen, Emmett Witchel, and Saman Amarasinghe,
    In Proceedings of 11th International Conference on Parallel Architectures and Compilation Techniques (PACT), Charlottesville, VA, September, 2002.

 

  1. Secure Execution Via Program Shepherding
    Vladimir Kiriansky, Derek Bruening, and Saman Amarasinghe.
    In Proceedings of the 11th USENIX Security Symposium, San Francisco, August 5, 2002.

 

  1. Providing Web Search Capability for Low-Connectivity Communities
    Libby Levison, William Thies, and Saman Amarasinghe.
    In Proceedings of the 2002 International Symposium on Technology and Society, Raleigh, North Carolina, June, 2002.

 

  1. The Raw Microprocessor: A Computational Fabric for Software Circuits and General Purpose Programs
    Michael Taylor, Jason Kim, Jason Miller, David Wentzlaff, Fae Ghodrat, Benjamin Greenwald, Henry Hoffman, Jae-Wook Lee, Paul Johnson, Walter Lee, Albert Ma, Arvind Saraf, Mark Seneski, Nathan Shnidman, Volker Strumpen, Matthew Frank, Saman Amarasinghe, and Anant Agarwal.
    In IEEE Micro, May, 2002.

 

  1. Searching the World Wide Web in Low-Connectivity Communities
    William Thies, Janelle Prevost, Tazeen Mahtab, Genevieve T. Cuevas, Saad Shakhshir, Alexandro Artola, Binh D. Vo, Yuliya Litvak, Sheldon Chan, Sid Henderson, Mark Halsey, Libby Levison, and Saman Amarasinghe.
    In the proceedings of the 11th International World Wide Web Conference, Global Community Track, Honolulu, Hawaii, May, 2002.

 

  1. StreamIt: A Language for Streaming Applications
    William Thies, Michal Karczmarek, and Saman Amarasinghe.
    In the proceedings of the 2002 International Conference on Compiler Construction. Š 2002 Springer-Verlag LNCS, Grenoble, France, April, 2002.

 

  1. Efficient Pipelining of Nested Loops: Unroll-and-Squash
    Darin Petkov, Randolph Harr, and Saman Amarasinghe.
    In the proceedings of the 16th International Parallel and Distributed Processing Symposium, Fort Lauderdale, Florida, April, 2002.

 

  1. Gigabit IP Routing on Raw
    Gleb A. Chuvpilo, David Wentzlaff, and Saman Amarasinghe
    In the Proceedings of the 1st HPCA Workshop on Network Processors, Cambridge, Massachusetts, February, 2002, pp. 2-9.

 

2001

  1. Design and Implementation of a Dynamic Optimization Framework for Windows, (Click here for PostScript)
    Derek Bruening, Evelyn Duesterwald, and Saman Amarasinghe.
    Proceedings of the 4th ACM Workshop on Feedback-Directed and Dynamic Optimization (FDDO),  Austin, Texas, December, 2001.

 

  1. The Raw Architecture: Signal Processing on a Scalable Composable Computation Fabric
    David Wentzlaff, Michael Bedford Taylor, Jason Kim, Jason Miller, Fae Ghodrat, Ben Greenwald, Paul Johnson, Walter Lee, Albert Ma, Nathan Shnidman, Henry Hoffmann, Arvind Saraf, Volker Strumpen, Matt Frank, Saman Amarasinghe, and Anant Agarwal,
    Proceedings of the Fifth Annual Workshop on High Performance Embedded Computing (HPEC), Boston, Massachusetts, November 2001.

 

  1. Compiler Support for Scalable and Efficient Memory Systems (click here for postscript)
    Rajeev Barua, Walter Lee, Saman Amarasinghe, Anant Agarwal,
    IEEE Transaction on Computers, , September, 2001. (A Special Issue on High Performance Memory Systems)

 

  1. The Raw Processor: A Composeable 32-Bit Fabric for Embedded and General Purpose Computing,
    M. Taylor, J. Kim, J. Miller, F. Ghodrat, B. Greenwald, P. Johnson, W. Lee, A. Ma, N. Schnidman, D. Wentzlaff, M. Frank, S. Amarasinghe, A. Agarwal,
    Proceedings of the Thirteenth Symposium on High Performance Chips (Hot Chips), Stanford, California, August 2001.

 

  1. Strength Reduction of Integer Division and Modulo Operations (Click here for PostScript)
    Jeffrey Sheldon, Walter Lee, Benjamin Greenwald, and Saman Amarasinghe.
    Proceedings of the '01 Languages and Compilers for Parallel Computing (LCPC), Cumberland Falls, Kentucky, August 2001.

 

  1. The TEK Search Engine (Click here for PostScript)
    Libby Levison, Bill Thies, Saman Amarasinghe.
    Proceedings of the Development by Design Workshop, Boston, MA, July 2001.

 

  1. A Unified Framework for Schedule and Storage Optimization (Click here for PostScript)
    William Thies, Frédéric Vivien, Jeffrey Sheldon, and Saman Amarasinghe.
    Proceedings of the SIGPLAN '01 Conference on Programming Language Design and Implementation (PLDI), Snowbird, Utah, June 2001.

 

2000

  1. Softspec: Software-based Speculative Parallelism. (Click here for PostScript)
    Derek Bruening, Srikrishna Devabhaktuni, and Saman Amarasinghe.
    Proceedings of the 3rd ACM Workshop on Feedback-Directed and Dynamic Optimization (FDDO), Monterey, California, December, 2000.

 

  1. FlexCache: A Framework for Flexible Compiler Generated Data Caching (click here for PostScript)
    Csaba Andras Moritz, Matthew Frank, and Saman Amarasinghe.
    Proceedings of the 2nd Workshop on Intelligent Memory Systems, Boston, MA, November, 2000.

 

  1. Bitwidth Analysis with Application to Silicon Compilation (click here for postscript),
    Mark Stephenson, Jonathan Babb, Saman Amarasinghe,
    Proceedings of the ACM SIGPLAN '2000 Conference on Programming Language Design and Implementation (PLDI), Vancouver, BC, June 2000.

 

  1. Exploiting Superword Level Parallelism with Multimedia Instruction Sets (click here for postscript),
    Sam Larsen, Saman Amarasinghe,
    Proceedings of the ACM SIGPLAN '2000 Conference on Programming Language Design and Implementation (PLDI), Vancouver, BC, June 2000.

 

1999

  1. Maps: A Compiler-Managed Memory System for Raw Machines,
    Rajeev Barua, Walter Lee, Saman Amarasinghe, and Anant Agarwal.
    Proceedings of the Twenty-Sixth International Symposium on Computer Architecture (ISCA), Atlanta, GA, May, 1999.

 

  1. Memory Parallelizing Applications Into Silicon
    Jonathan Babb, Martin Rinard, Andras Moritz, Walter Lee, Matthew Frank, Rajeev Barua, and Saman Amarasinghe.
    Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines '99 (FCCM), Napa Valley, CA, April 1999.

 

1998

  1. Memory Bank Disambiguation using Modulo Unrolling for Raw Machines,
    Rajeev Barua, Walter Lee, Saman Amarasinghe, and Anant Agarwal.
    Proceedings of the Fifth International Conference on High Performance Computing, December, 1998.

 

  1. Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine,
    Walter Lee, Rajeev Barua, Matthew Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar and Saman Amarasinghe,
    Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October, 1998.

 

1997

  1. Baring it all to Software: Raw Machines.
    Elliot Waingold, Michael Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman Amarasinghe, and Anant Agarwal.
    IEEE Computer 30(9), September 1997. (A Special Issue on Billion Transistor Architectures)

 

  1. The Raw Compiler Project.
    Anant Agarwal, Saman Amarasinghe, Rajeev Barua, Matthew Frank, Walter Lee, Vivek Sarkar, Devabhaktuni Srikrishna, and Michael Taylor.
    Proceedings of the Second SUIF Compiler Workshop, Stanford, CA, August, 1997.

 

1996

  1. Maximizing Multiprocessor Performance with the SUIF Compiler.
    M. W. Hall, J. M. Anderson, S. P. Amarasinghe, B. R. Murphy, S.-W. Liao, E. Bugnion and M. S. Lam.
    IEEE Computer, 29(12), December 1996. (A Special Issue on Multiprocessors)

 

  1. The Multiprocessor as a General-Purpose Processor: A Software Perspective.
    Saman P. Amarasinghe, Jennifer M. Anderson, Chris S. Wilson, Shih-Wei Liao, Robert S. French, Mary W. Hall, Brian R. Murphy and Monica S. Lam.
    IEEE Micro 16(3), June 1996. (A Special Issue on the Hot Chips VII Conference, Stanford, CA, Aug. 1995).

 

1995

  1. Detecting Coarse-Grain Parallelism Using an Interprocedural Parallelizing Compiler (Click here for PostScript)
    M. W. Hall, S. P. Amarasinghe, B. R. Murphy, S. Liao, and M. S. Lam.
    Proceedings of Supercomputing '95, December 1995.

 

  1. Interprocedural Analysis for Parallelization(Click here for PostScript)
    M. W. Hall, B. R. Murphy, S. P. Amarasinghe, S. Liao, and M. S. Lam.
    Proceedings of the 8th International Workshop on Languages and Compilers for Parallel Computing (LCPC), August 1995.

 

  1. Breakthroughs in Parallelizing Compilers and Their Architectural Implications,
    S. P. Amarasinghe, J. A. M. Anderson, R. S. French, M. W. Hall,  M. S. Lam, S. W. Liao, B. R. Murphy, C. W. Tseng, C. S. Wilson,  R. P. Wilson,
    Proceedings of the Seventh Symposium on High-Performance Chips (Hot Chips), Stanford, CA, August 1995.

 

  1. Data and Computation Transformations for Multiprocessors (Click here for PostScript)
    J. M. Anderson, S. P. Amarasinghe and M. S. Lam.
    Proceedings of the Fifth ACM SIGPLAN Symposium on Principles and Practice of Parallel Processing, July 1995.

 

  1. Unified Compilation Techniques for Shared and Distributed Address Space Machines
    C.-W. Tseng, J. M. Anderson, S. P. Amarasinghe, and M. S. Lam.
    Proceedings of the International Conference on Supercomputing, July 1995.

 

  1. The SUIF Compiler for Scalable Parallel Machines
    S. P. Amarasinghe, J. M. Anderson, M. S. Lam and C. W. Tseng
    Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing, February 1995.

 

  1. Interprocedural Parallelization Analysis: A Case Study
    M. W. Hall, B. R. Murphy and S. P. Amarasinghe
    Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing, February 1995.

 

1993

  1. Communication Optimization and Code Generation for Distributed Memory Machines
    S. P. Amarasinghe and M. S. Lam.
    Proceedings of the ACM SIGPLAN'93 Conference on Programming Language Design and Implementation (PLDI), June 1993.

 

  1. An Overview of a Compiler for Scalable Parallel Machines
    S. P. Amarasinghe, J. M. Anderson, M. S. Lam and A. W. Lim.
    Proceedings of the 6th Workshop on Languages and Compilers for Parallel Computing (LCPC), August 1993.

 

  1. Array Data Flow Analysis and its Use in Array Privatization
    D. E. Maydan, S. P. Amarasinghe and M. S. Lam.
    Proceedings of The 20th Annual ACM Symposium on Principles of Programming Languages (POPL), January 1993.

 

1992

  1. Data Dependence and Data-Flow Analysis of Arrays
    D. E. Maydan, S. P. Amarasinghe and M. S. Lam.
    Proceedings of 5th Workshop on Languages and Compilers for Parallel Computing (LCPC), 1992.


Technical Reports

  1. Phased Computation Graphs in the Polyhedral Model,
    William Thies, Jasper Lin, and Saman Amarasinghe.
    MIT/LCS Technical Memo LCS-TM-630, August, 2002.

 

  1. A Stream Compiler for Communication-Exposed Architectures,
    Michael Gordon, William Thies, Michal Karczmarek, Jeremy Wong, Henry Hoffman, David Z. Maze, and Saman Amarasinghe.
    MIT/LCS Technical Memo LCS-TM-627, May 2002.

 

  1. Secure Execution Via Program Shepherding,
    Vladimir Kiriansky, Derek Bruening, and Saman Amarasinghe.
    MIT/LCS Technical Memo LCS-TM-625, February, 2002.

 

  1. StreamIt: A Compiler for Streaming Applications,
    William Thies, Michal Karczmarek, Michael Gordon, David Z. Maze, Jeremy Wong, Henry Hoffman, Matthew Brown, and Saman Amarasinghe.
    MIT/LCS Technical Memo LCS-TM-622, December, 2001.

 

  1. Techniques for Increasing and Detecting Memory Alignment,
    Samuel Larsen, Emmett Witchel, and Saman Amarasinghe
    MIT/LCS Technical Memo LCS-TM-621, November, 2001.

 

  1. StreaMIT: A Language for Streaming Applications,
    Bill Thies, Michal Karczmarek, and Saman Amarasinghe,
    MIT/LCS Technical Memo MIT-LCS-TM-620, August 2001.

 

  1. A Software Framework for Supporting General Purpose Applications on Raw Computation Fabrics,
    Matthew Frank, Walter Lee and Saman Amarasinghe,
    MIT-LCS Technical Memo MIT-LCS-TM-619, July 2001.

 

  1. Perspectives on the Use of Internet in Sri Lanka,
    Govinda Shrestha, and Saman Amarasinghe,
    MIT/LCS Technical Report MIT-LCS-TR-815, January 2001.

 

  1. A Unified Framework for Schedule and Storage Optimization,
    William Thies, Frédéric Vivien, Jeffrey Sheldon, Saman Amarasinghe,
    MIT/LCS Technical Memo MIT-LCS-TM-613, November 2000.

 

  1. Softspec: Software-based Speculative Parallelism,
    Derek Bruening, Srikrishna Devabhaktuni, and Saman Amarasinghe,
    MIT/LCS Technical Memo, MIT-LCS-TM-606, April 2000.

 

  1. Strength Reduction of Integer Division and Modulo Operations,
    Walter Lee, Benjamin Greenwald, Saman Amarasinghe,
    MIT/LCS Technical Memo MIT-LCS-TM-600, November, 1999.

 

  1. Exploiting Superword Level Parallelism with Multimedia Instruction Sets (Click here for Postscript),
    Sam Larsen, Saman Amarasinghe,
    MIT/LCS Technical Memo MIT-LCS-TM-601, November, 1999.

 

  1. Bitwidth Analysis with Application to Silicon Compilation (Click here for Postscript),
    Mark Stephenson, Jonathan Babb, Saman Amarasinghe,
    MIT/LCS Technical Memo MIT-LCS-TM-602, November, 1999.

 

  1. Hot Pages: Software Caching for Raw Microprocessors (Click here for Postscript),
    Csaba Andras Moritz, Matthew Frank, Walter Lee,and Saman Amarasinghe,
    MIT/LCS Technical Memo MIT-LCS-TM-599, August, 1999.

 

  1. SUDS: Primitive Mechanisms for Memory Dependence Speculation,
    M. Frank, C. A. Moritz, B. Greenwald, S. Amarasinghe, and A. Agarwal,
    MIT/LCS Technical Memo MIT-LCS-TM-591, January, 1999.

 

  1. Parallelizing Applications into Smart Memories,
    Jonathan Babb, Martin Rinard, Csaba Andras Moritz, Walter Lee, Matthew Frank, Rajeev Barua, Saman Amarsinghe,
    MIT/LCS Technical Report MIT-LCS-TR-769, October, 1998.

 

  1. Maps: A Compiler-Managed Memory System for Raw Machines,
    Rajeev Barua, Walter Lee, Saman Amarasinghe and Anant Agarwal.
    MIT/LCS Technical Memo MIT-LCS-TM-583, July, 1998.

 

  1. Memory Bank Disambiguation using Modulo Unrolling for Raw Machines,
    Rajeev Barua, Walter Lee, Saman Amarasinghe and Anant Agarwal.
    MIT/LCS Technical Report MIT-LCS-TR-759, June, 1998.

 

  1. Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine,
    Walter Lee, Rajeev Barua, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman Amarasinghe, Anant Agarwal
    MIT/LCS Technical Memo MIT-LCS-TM-572, December, 1997.

 

  1. Baring it all to Software: The Raw Machine,
    Elliot Waingold, Michael Taylor, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Srikrishna Devabhaktuni, Rajeev Barua, Jonathan Babb, Saman Amarasinghe, and Anant Agarwal
    MIT/LCS Technical Report MIT-LCS-TR-709, March 1997.

 

  1. Parallelizing Compiler Techniques Based on Linear Inequalities. (Click here for pdf)
    S. P. Amarasinghe, Ph.D. thesis,
    Technical Report CSL-TR-97-714, Stanford University, January, 1997.

 

  1. Interprocedural parallelization analysis: Preliminary results.
    M. W. Hall, S. P. Amarasinghe, B. R. Murphy, S.-W. Liao, and M. S. Lam.
    Technical Report CSL-TR-95-665, Dept. of Computer Science, Stanford University, March 1995.


Miscellaneous Papers

  1. A Common Machine Language for Grid-Based Architectures
    William Thies, Michal Karczmarek, Michael Gordon, David Z. Maze, Jeremy Wong, Henry Hoffman, Matthew Brown, and Saman Amarasinghe.
    In ACM SIGARCH Computer Architecture News, June, 2002.

 

  1. SUIF: A Parallelizing and Optimizing Research Compiler
    R. Wilson, R. French, C. Wilson, S. Amarasinghe, J. Anderson, S. Tjiang, S.-W. Liao, C.-W. Tseng, M. Hall, M. Lam, and J. Hennessy.
    ACM SIGPLAN Notices, 29(12):31-37, December 1994.

 

INVITED TALKS AND PANELS

  1. November 2005, "Security: The Application Point of View", Panelist, CSI 32nd Annual Computer Security Conference, Washington DC.


 

  1. October 2005, "TEK: Internet Search System for Low-Connectivity Communities", Keynote Speech, Technology and Infrastructure for Emerging Regions (TIER) Workshop, Berkeley, CA.


 

  1. October 2005, "View from the Labs", Panelist, DowJones Emerging Ventures Conference. Boston, MA.


 

  1. May 2005, "Characteristics of an Entrepreneur", Panelist, California Turkish American Business Conference, Palo Alto, CA.


 

  1. April 2005, "New Technologies Showcase", Panelist, Global Security Consortium Summit, Washington DC.


 

  1. March 2005, "StreamIt: A Language and Compiler for the Streaming Domain," Seminar on Scheduling for Parallel Architectures: Theory, Applications, Challenges, Schloss Dagstuhl International Conference and Research Center for Computer Science, Dagstuhl, Germany.


 

  1. March 2005, "Convergent Scheduling," Seminar on Scheduling for Parallel Architectures: Theory, Applications, Challenges, Schloss Dagstuhl International Conference and Research Center for Computer Science, Dagstuhl, Germany.


 

  1. March 2005, "Multicores from the Compiler's Perspective: A Blessing or a Curse?", Keynote Speech, International Symposium on Code Generation and Optimization (CGO), San Jose, CA.


 

  1. November 2004, "Defeating Worm Attacks using a Memory Firewall", Security SIG, SDForum, Palo Alto, CA


 

  1. October 2003, "StreamIt: A Language and Compiler for the Streaming Domain," University of Illinois at Urbana Champaign, IL.


 

  1. October 2003, "Alternative Solutions to Two Hard Compiler Problems,", Stanford University, Stanford, CA.


 

  1. October 2003, "Secure Program Execution," 10th Annual Research and Development Conference, MIT, Cambridge, MA.


 

  1. September 2003, "Architectures, Languages, and Compilers for the Streaming Domain," Tutorial at the 12th Annual International Conference on Parallel Architectures and Compilation Techniques, New Orleans, Louisiana.


 

  1. August 2003, "StreamIt: A Language and Compiler for the Streaming Domain," Workshop on Streaming Systems, Dedham, MA.


 

  1. June 2003, "StreamIt: A Streaming Language for Modern Architectures," Research Day Invited Talk, Ecole Polytechnique Federale De Lausanne (EPFL), Lausanne, Switzerland.


 

  1. June 2003, "Challenges for Computer Architects: Breaking the Abstraction Barriers," NSF Future of Computer Architecture Research Panel, San Diego, CA.


 

  1. April 2003, "Secure Execution via Program Shepherding," Harvard University, Cambridge, MA.


 

  1. March 2003, "On the Run - Building Dynamic Program Modifiers for Optimization, Introspection and Security," Tutorial at the First International Symposium on Code Generation and Optimization (CGO), San Francisco, CA.


 

  1. March 2003, "Secure Execution via Program Shepherding," University of California, Berkeley, CA.


 

  1. March 2003, "Secure Execution via Program Shepherding," Cornell University, Ithaca, NY.


 

  1. February 2003, "Secure Execution via Program Shepherding," University of California at San Diego, San Diego, CA.


 

  1. January 2003, "Secure Execution via Program Shepherding," National University of Singapore, Singapore.


 

  1. January 2003, "Defying the Speed of Light with Wire-Exposed Architectures and Spatially-Aware Compilers," Nanyang Technological University, Singapore.


 

  1. January 2003, "StreamIt: A Language and Compiler for Communication-Exposed Architectures," The SMA Forum, Singapore.


 

  1. January 2003, "Secure Execution via Program Shepherding," University of Washington, Seattle, WA.


 

  1. December 2002, "Secure Execution via Program Shepherding," Princeton University, Princeton, NJ.


 

  1. December 2002, "Secure Execution via Program Shepherding," Microsoft Research Laboratories, Redmond, WA.


 

  1. October 2002, "Defying the Speed of Light with Spatially Aware Computing," ASIAN Symposium on Partial Evaluation and Semantic-Based Program Manipulation, Aizu, Japan.


 

  1. October 2002, "On the Run - Building Dynamic Program Modifiers for Optimization, Introspection and Security," Tutorial at the Tenth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA.


 

  1. October 2002, "Defying the Speed of Light with Wire-Exposed Architectures and Spatially-Aware Compilers," Georgia Tech., Atlanta, GA.


 

  1. October 2002, "Defying the Speed of Light with Wire-Exposed Architectures and Spatially-Aware Compilers," IBM Research Laboratories, Yorktown Heights, NY.


 

  1. October 2002, "DynamoRIO: Dynamic Program Modification System and its use in Program Shepherding and Optimization," Intel Corporation, Shrewsbury, MA.


 

  1. October 2002, "DynamoRIO: Dynamic Program Modification System and its use in Program Shepherding and Optimization," Hewlett-Packard Company, Nashua, NH.


 

  1. August 2002, "Secure Execution via Program Shepherding," Hewlett Packard Laboratories, Palo Alto, CA.


 

  1. August 2002, "Defying Speed of Light: Spatially-Aware Compiler for Wire-Exposed Architectures," Intel Research Laboratories, Santa Clara, CA.


 

  1. August 2002, "Secure Execution via Program Shepherding," VMWare, Inc., Palo Alto, CA.


 

  1. June 2002, "On the Run: Building Dynamic Program Modifiers for Optimization, Introspection and Security," Tutorial at Programming Language Design and Implementation Conference (PLDI) with Evelyn Duesterwald, Berlin Germany.


 

  1. May 2002, "Wire-Exposed Architectures and Spatially-Aware Compilers," ITRI, Taiwan ROC.


 

  1. January 2002, "Alignment Analysis," Colombo University, Colombo, Sri Lanka.


 

  1. January 2002, "The Raw Architecture," University of Moratuwa, Colombo, Sri Lanka.


 

  1. January 2002, "Alignment Analysis," Indian Institute of Technology, Chennai, India.


 

  1. January 2002, "Alignment Analysis," Stanford University, Stanford, CA.


 

  1. October 2001, "Alignment Analysis," Computer Architecture Seminar Series, University of Texas - Austin, TX.


 

  1. September 2000, "Practical Compiler Techniques for Detecting Parallelism," Electrical and Computer Engineering Department Colloquium, Boston University, Boston, MA.


 

  1. July 2000, "Practical Techniques for Detecting Parallelism," University of Illinois at Urbana-Champaign, IL.


 

  1. June 2000, "Softspec: Software-based Speculative Parallelism," Microsoft Laboratories, Seattle, WA.


 

  1. February 2000, "Compiling for Multimedia Instruction Sets with Superword Level Parallelism," MIT EECS Colloquium, Cambridge, MA.


 

  1. February 2000, "Compiling for Multimedia Instruction Sets with Superword Level Parallelism," Hewlett-Packard Laboratories, Cambridge, MA.


 

  1. December 1999, "Superword Level Parallelism," Princeton University, Princeton, NJ.


 

  1. January 1999, "Compiling for a RAW Machine," Compaq Corporation, MA.


 

  1. February 1998, "The RAW Architecture," Carnegie Mellon University, Pittsburgh, PA.

AWARDS, GRANTS AND CONTRACTS

Exploiting PCA Architectures for Cognitive Applications.
Defense Advanced Research Projects Agency, Seedling.
Saman Amarasinghe, Anant Agarwal.
May 2003 – April 2004.

PCA Raw Fabric: Architectural Prototyping, Demonstration and Evaluation.
Defense Advanced Research Projects Agency, PCA II.
Saman Amarasinghe, Anant Agarwal.
January 2003 – September 2005

Raw Supercomputer Project Collaboration.
ITRI, Taiwan.
Anant Agarwal, Saman Amarasinghe.
January 2003 – December 2003

Dynamic Optimization, and its Application to Domain-Specific Languages, Phase I
Hewlett-Packard Corporation
Saman Amarasinghe, Greg Sullivan
February 2002 - February 2004

Raw Fabric: A Technology for Rapid Embedded-System Customization.
Defense Advanced Research Projects Agency, PCA.
Saman Amarasinghe, Anant Agarwal.
June 2001 – May 2003.

Faculty Fellowship.
University of Singapore.
Saman Amarasinghe.
January 2001 – December 2002.

CISE Experimental Partnerships: The MIT Raw Machine.
National Science Foundation EIA-0071841.
Saman Amarasinghe, Anant Agarwal, Martin Rinard.
September 2000 – September 2002.

Exploiting Superword Level Parallelism.
National Science Foundation CCR-0073510.
Saman Amarasinghe.
June 2000 – May 2003.

PACE: Power Aware Computing Engines.
Defense Advanced Research Projects Agency, PAC/C, F30602-00-2-0562.
Krste Asanovic, Saman Amarasinghe, Martin Rinard.
May 2000 – September 2003.

Compilation Techniques for Embedded Processors.
MIT/LCS Project Oxygen.
Saman Amarasinghe.
May 2000 – April 2002.

Baring it all to Software.
National Science Foundation. EIA-9810173.
Anant Agarwal, Saman Amarasinghe, Martin Rinard.
October 1998 – September 2001.

DISSERTATION

Paralelizing Compiler Techniques Based on Linear Inequalities.

Shared-memory multiprocessors, built out of the latest microprocessors, are becoming a prevalent computer architecture. To effectively harness the power of these machines it is important that we find all the available parallelism in the programs. We have developed an interprocedural optimizer with novel array analysis techniques. We have shown that these analyses in combination with a full suite of scalar analyses can be successful in finding large amounts of parallelism in general scientific applications. Another important factor in obtaining parallel performance is the effective utilization of the memory hierarchy. In parallel applications false sharing and cache conflicts between processors can significantly reduce performance. We have developed the first compiler that automatically performs a full suite of data transformations (a combination of transpose, strip-mining and padding). We have shown that the performance of many benchmarks are drastically improved after the data transformations.

Full text: (postscript, pdf)

Advisor: Professor Monica Lam, Stanford University.